04042cam a2200409 a 4500 1/38349 090923s2008 ne 001 0 eng 9780123739735 012373973X 9780080556802 (electronic bk.) 0080556809 (electronic bk.) 40990 OPELS eng OPELS OCLCQ N$T YDXCP IDEBK E7B UMI CEF NHM DEBSZ DKDLA KNOVL OCLCO OCLCQ KNOVL OCLCQ GR-PeUP System-on-chip test architectures : nanometer design for testability / edited by Laung-Terng Wang, Charles E. Stroud, Nur A. Touba. Amsterdam ; Boston : Morgan Kaufmann Publishers, c2008. 1 online resource (xxxvi, 856 p.) : ill. The Morgan Kaufmann series in systems on silicon Διαθέσιμο και σε ηλεκτρονικό βιβλίο, τρόπος πρόσβασης μέσω διαδικτύου. Modern electronics testing has a legacy of more than 40 years. The introduction of new technologies, especially nanometer technologies with 90nm or smaller geometry, has allowed the semiconductor industry to keep pace with the increased performance-capacity demands from consumers. As a result, semiconductor test costs have been growing steadily and typically amount to 40% of today?s overall product cost. This book is a comprehensive guide to new VLSI Testing and Design-for-Testability techniques that will allow students, researchers, DFT practitioners, and VLSI designers to master quickly System-on-Chip Test architectures, for test debug and diagnosis of digital, memory, and analog/mixed-signal designs. KEY FEATURES * Emphasizes VLSI Test principles and Design for Testability architectures, with numerous illustrations/examples. * Most up-to-date coverage available, including Fault Tolerance, Low-Power Testing, Defect and Error Tolerance, Network-on-Chip (NOC) Testing, Software-Based Self-Testing, FPGA Testing, MEMS Testing, and System-In-Package (SIP) Testing, which are not yet available in any testing book. * Covers the entire spectrum of VLSI testing and DFT architectures, from digital and analog, to memory circuits, and fault diagnosis and self-repair from digital to memory circuits. * Discusses future nanotechnology test trends and challenges facing the nanometer design era; promising nanotechnology test techniques, including Quantum-Dots, Cellular Automata, Carbon-Nanotubes, and Hybrid Semiconductor/Nanowire/Molecular Computing. * Practical problems at the end of each chapter for students. Introduction; Digital Test Architectures; Fault-Tolerant Design; SOC/NOC Test Architectures; SIP Test Architectures; Delay Testing; Low-Power Testing; Coping with Physical Failures, Soft Errors, and Reliability Issues; Design for Manufacturability and Yield; Design for Debug and Diagnosis; Software-Based Self-Testing; FPGA Testing; MEMS Testing; High-Speed I/O Interface; Analog and Mixed-Signal Test Architectures; RF Testing; Testing Aspects of Nanotechnology Trends. Includes bibliographical references and index. Systems on a chip Testing. Integrated circuits Very large scale integration Testing. Integrated circuits Very large scale integration Design. VLSI. Electronic books. Wang, Laung-Terng. Stroud, Charles E. Touba, Nur A. Morgan Kaufmann series in systems on silicon. INST UNIPILB EBOOKS 20100705 00b40853 00b40853 ONLINE 0 INST UNIPILB MAIN 20090923 621.39'5 SYS 00159129 00159129 LOAN 0 1 ScienceDirect http://www.sciencedirect.com/science/book/9780123739735 /webopac/covers/02/40990_9780123739735.jpg /webopac/covers/02/40990_012373973X.jpg /webopac/covers/02/40990_9780080556802.jpg (electronic bk.) /webopac/covers/02/40990_0080556809.jpg (electronic bk.)