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    <title>Αποτελέσματα για "Integrated circuits Very large scale integration Testing."</title>
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      <title>VLSI testing : digital and mixed analoque/digital techniques /</title>
      <pubDate>Thu, 01 Jan 1998 03:28:38 +0200</pubDate>
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      <author>Hurst, Stanley L.</author>
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      <dc:date>1998</dc:date>
      <dc:creator>Hurst, Stanley L.</dc:creator>
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      <title>Essentials of electronic testing for digital, menory and mixed-signal VLSI circuits /</title>
      <pubDate>Sat, 01 Jan 2000 03:28:38 +0200</pubDate>
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      <author>Bushnell, Michael L. 1950-</author>
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      <dc:date>2000</dc:date>
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      <title>From contamination to defects, faults and yield loss : Simulation and applications /</title>
      <pubDate>Mon, 01 Jan 1996 03:28:38 +0200</pubDate>
      <link>http://okeanos.lib.unipi.gr/Record/1%2F23233</link>
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      <author>Khare, Jitendra B.</author>
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      <dc:date>1996</dc:date>
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      <title>Introduction to IDDQ testing /</title>
      <pubDate>Wed, 01 Jan 1997 03:28:38 +0200</pubDate>
      <link>http://okeanos.lib.unipi.gr/Record/1%2F23242</link>
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      <dc:date>1997</dc:date>
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      <title>Delay fault testing for VLSI circuits/</title>
      <pubDate>Thu, 01 Jan 1998 03:28:38 +0200</pubDate>
      <link>http://okeanos.lib.unipi.gr/Record/1%2F23247</link>
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      <author>Krstic, Angela 1965-</author>
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      <dc:date>1998</dc:date>
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      <title>Power-constrained testing of VLSI circuits/</title>
      <pubDate>Wed, 01 Jan 2003 03:28:38 +0200</pubDate>
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      <author>Nicolici, Nicola.</author>
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      <title>VLSI test principles and architectures : design for testability /</title>
      <pubDate>Sun, 01 Jan 2006 03:28:38 +0200</pubDate>
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      <title>System-on-chip test architectures : nanometer design for testability /</title>
      <pubDate>Tue, 01 Jan 2008 03:28:38 +0200</pubDate>
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