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|a 047198325X
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|l 20171
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| 040 |
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|a DLC
|b GR-PeUP
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| 082 |
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|a 621.39'5 RU
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| 100 |
1 |
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|a Rushton Andrew.
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| 245 |
1 |
0 |
|a VHDL for logic synthesis /
|c Andrew Rushton
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| 250 |
|
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|a 2nd ed.
|
| 260 |
|
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|a Chichester :
|b Wiley,
|c 1998
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| 300 |
|
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|a xiii, 375 p. :
|b ill. ;
|c 26 cm.
|
| 504 |
|
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|a Includes bibliographical references and index
|
| 650 |
|
4 |
|a VHDL (Computer hardware description language).
|
| 650 |
|
4 |
|a Logic design
|x Data processing.
|
| 650 |
|
4 |
|a Computer
|x aided design.
|
| 852 |
|
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|a INST
|b UNIPILB
|c MAIN
|e 20040709
|h 621.39'5 RU
|p 00141094
|q 00141094
|t LOAN
|y 0
|4 1
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| 856 |
4 |
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|d /webopac/covers/01/20171_047198325X.jpg
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