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|a 1402076525
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| 035 |
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|l 24794
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| 040 |
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|a DLC
|b GR-PeUP
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| 082 |
0 |
0 |
|a 621.39'5 RAD
|
| 100 |
1 |
|
|a Radecka, Katarzyna.
|
| 245 |
1 |
0 |
|a Verification by error modeling :
|b using testing techniques in hardware verification /
|c Radecka Katarzyna, Zilic, Zeljko.
|
| 260 |
|
|
|a Boston :
|b Kluwer Academic,
|c 2003.
|
| 300 |
|
|
|a xiv, 216 p. :
|b ill. ;
|c 25 cm.
|
| 490 |
1 |
|
|a Frontiers in electronic testing ;
|
| 504 |
|
|
|a Includes bibliographical references and index.
|
| 650 |
|
4 |
|a Integrated circuits
|x Very large scale integration
|x Computer-aided design.
|
| 650 |
|
4 |
|a Integrated circuits
|x Verification.
|
| 650 |
|
4 |
|a Error analysis (Mathematics)
|
| 700 |
1 |
|
|a Zilic, Zeljko.
|
| 830 |
|
|
|a Frontiers in electronic testing ;
|v 25
|
| 852 |
|
|
|a INST
|b UNIPILB
|c MAIN
|e 20040915
|h 621.39'5 RAD
|p 00143843
|q 00143843
|t LOAN
|y 0
|4 1
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| 856 |
4 |
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|d /webopac/covers/02/24794_1402076525.jpg
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