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061106s2003 njua b i 001 0 eng |
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|a 0130891614
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| 035 |
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|l 33661
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| 040 |
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|a DLC
|b GR-PeUP
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| 082 |
0 |
0 |
|a 621.39'5 CIL
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| 100 |
1 |
|
|a Ciletti, Michael D.
|
| 245 |
1 |
0 |
|a Advanced digital design with the Verilog HDL /
|c Michael D. Ciletti
|
| 260 |
|
|
|a Upper Saddle River, NJ :
|b Prentice Hall,
|c 2003
|
| 300 |
|
|
|a xxi, 982 σ. :
|b εικ. ;
|c 24 εκ.
|e + 3 CD-ROM
|
| 500 |
|
|
|a Περιέχει SILOS 2001
|
| 504 |
|
|
|a Περιέχει βιβλιογραφία και ευρετήριο
|
| 650 |
|
4 |
|a Digital electronics.
|
| 650 |
|
4 |
|a Logic circuits
|x Computer-aided design.
|
| 650 |
|
4 |
|a Verilog (Computer hardware description language)
|
| 830 |
|
|
|a Prentice Hall Xilinx design series.
|
| 852 |
|
|
|a INST
|b UNIPILB
|c MAIN
|e 20061106
|h 621.39'5 CIL
|p 00151281
|q 00151281
|t LOAN
|y 0
|4 1
|
| 856 |
4 |
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|d /webopac/covers/02/33661_0130891614.jpg
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