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|a 1401840302
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| 035 |
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|l 37994
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| 040 |
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|a DLC
|b GR-PeUP
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| 082 |
0 |
0 |
|a 621.39'5 DUE
|
| 100 |
1 |
|
|a Dueck, Robert K.
|
| 245 |
1 |
0 |
|a Digital design with CPLD applications and VHDL /
|c Robert K. Dueck.
|
| 260 |
|
|
|a Clifton Park :
|b Thomson/Delmar Learning,
|c 2005.
|
| 300 |
|
|
|a xx, 1004 σ. :
|b εικ. ;
|c 26 εκ. +
|e 1 οπτικό δίσκο Η/Υ.
|
| 500 |
|
|
|a Περιέχει ευρετήριο.
|
| 650 |
|
4 |
|a Programmable logic devices
|x Design and construction.
|
| 650 |
|
4 |
|a Programmable array logic.
|
| 650 |
|
4 |
|a VHDL (Computer hardware description language).
|
| 852 |
|
|
|a INST
|b UNIPILB
|c MAIN
|e 20080926
|h 621.39'5 DUE
|p 00156347
|q 00156347
|t LOAN
|y 0
|4 1
|
| 856 |
4 |
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|d /webopac/covers/02/37994_1401840302.jpg
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