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040524s1998 enka 001 0 eng |
| 020 |
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|a 9780792381846
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| 035 |
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|l 24783
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| 040 |
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|a DLC
|b GR-PeUP
|
| 082 |
0 |
0 |
|a 621.3815 HUA
|
| 100 |
1 |
|
|a Huang, Shi-Yu
|d , 1965-
|
| 245 |
1 |
0 |
|a Formal equivalence checking and design debugging /
|c by Shi-Yu Huang and Kwang-Ting (Tim) Cheng
|
| 260 |
|
|
|a Boston :
|b Kluwer Academic Publishers,
|c 1998
|
| 300 |
|
|
|a xviii, 229 σ.
|b εικ.;
|c 24 εκ.
|
| 504 |
|
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|a Περιλαμβάνει βιβλιογραφία και ευρετήριο
|
| 650 |
|
4 |
|a Integrated circuits
|x Verification.
|
| 650 |
|
4 |
|a Electronic circuit design
|x Data processing.
|
| 650 |
|
4 |
|a Application specific integrated circuits
|x Design and construction.
|
| 700 |
1 |
|
|a Cheng, Kwang-Ting
|d 1961-
|
| 852 |
|
|
|a INST
|b UNIPILB
|c MAIN
|e 20040913
|h 621.3815 HUA
|p 00143821
|q 00143821
|t LOAN
|y 0
|4 1
|
| 856 |
4 |
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|d /webopac/covers/02/24783_9780792381846.jpg
|
